Flip chip packaging structure and related packaging method

ABSTRACT

A bump is formed on a bonding pad provided on a substrate. A passivation film covering a bonding pad provided on a semiconductor chip is provided with two apertures in which bumps are formed. The bump provided on the substrate advances and enters into a clearance between these bumps provided on the semiconductor chip when the semiconductor chip is packaged with the substrate.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is based on and incorporates herein by referenceJapanese Patent Application No. 2003-185860 filed on Jun. 27, 2003.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a flip chip packaging structureand a related packaging method.

[0003] As shown in FIG. 19, a flip chip packaging technique isapplicable to a bonding structure between a semiconductor chip 110 and asubstrate 100. According to the structure shown in FIG. 19, a pad 111 isformed on an active face of the semiconductor chip 110. A bump 112,formed on the pad 111, serves as a bonding member for connecting the pad111 to the substrate 100. Furthermore, a pad 101, provided on thesubstrate 100, serves as a bonding member for connecting the substrate100 to the semiconductor chip 110. The bump 112 provided on the chip isconnected to the pad 101 provided on the substrate by thermocompressionbonding or ultrasonic welding.

[0004] It is a recent trend that the semiconductor chip 110 is highlyintegrated and accordingly the size W1 of the pad 111 provided on thesemiconductor chip 110 and a pitch P1 between two neighboring pads 111are very small. The size of the bump 112 formed on the pad 111 is small,correspondingly. When the semiconductor chip 110 is flip chip bonded tothe substrate 100 via the bump 112, it is necessary to adjust the sizeof the pad 101 formed on the substrate 100 so as to fit to the pitch P1of the pad 111 provided on the semiconductor chip 110. Accordingly, thesize of the pad 101 formed on the substrate 100 is small when the pitchbetween neighboring pads 111 provided on the semiconductor chip 110 isnarrow.

[0005] The semiconductor chip 110 and the substrate 100 are bonded inthe following manner.

[0006] First, by plating or with discharge, a ball is formed on the pad111 provided on an active face of the semiconductor chip 110. Then, theball is press welded to the pad 111 under given heat or ultrasonic waveso as to form the bump (i.e. projected electrode) 112 on the pad 111.

[0007] Then, the semiconductor chip 110 is mounted on the substrate 100under a condition that semiconductor chip 110 is faced down. The bump112 is mechanically and electrically bonded to the pad 101 provided onthe substrate 100 under applied heat and pressure. Furthermore, for thepurpose of enhancing the bonding reliability, a clearance between thesemiconductor chip 110 and the substrate 100 is filled with an underfillmember (e.g. a thermosetting epoxy resin) 120.

[0008] When the size Φ20 of the bump 112 is small, a gap G to be formedafter accomplishing the bonding operation between the semiconductor chip110 and the substrate 100 is small correspondingly. This results inreduction in a stress relaxing capability of the underfill member 120which can relax a thermal stress if caused due to a thermal expansioncoefficient difference between the substrate 100 and the semiconductorchip 100. Furthermore, a bonding area between the bump 112 and the pad101 provided on the substrate is small, which results in deteriorationin the bonding reliability against the above-described thermal stress.

[0009] From the foregoing reasons, this conventional bonding techniquecannot be preferably applied to electronic control apparatuses installedin engine rooms or any other devices which are subjected to severetemperature environments.

SUMMARY OF THE INVENTION

[0010] In view of the above-described problems, the present inventionhas an object to provide a flip chip packaging structure that is capableof improving the bonding reliability between a semiconductor chip and asubstrate. Furthermore, the present invention has an object to provide arelated flip chip packaging method.

[0011] In order to accomplish the above and other related objects, thepresent invention provides a first flip chip packaging structureincluding a bump formed on a first bonding pad provided on a surface ofa semiconductor chip and a second bonding pad provided on a substrate,wherein the first and second bonding pads are mutually connected byelectrically and mechanically bonding the first and second bonding padsvia the bump under a condition that the bump formed on the semiconductorchip is adjusted in position relative to the second bonding pad providedon the substrate, wherein a bump is formed on the second bonding padprovided on the substrate, at least two apertures are opened on apassivation film covering the first bonding pad provided on thesemiconductor chip, bumps are formed in respective apertures, and thebump provided on the substrate advances and enters into a clearancebetween the bumps provided on the semiconductor chip.

[0012] According to this arrangement, the bump provided on the substrateadvances and enters into the clearance between the bumps provided on thesemiconductor chip. The bonding area becomes large. Furthermore, aformed bonding surface is not parallel to a shearing direction of athermal stress to be produced due to a thermal expansion coefficientdifference between the substrate and the semiconductor chip. Thus, itbecomes possible to improve the bonding reliability between thesemiconductor chip and the substrate.

[0013] According to the flip chip packaging structure in accordance withthis invention, it is preferable that the bump formed on thesemiconductor chip is a bump formed by plating. This is advantageous inthat the shape of the bump can be formed accurately. Accordingly, theshape of a clearance can be formed accurately.

[0014] Preferably, the bump formed on the substrate is a stud bumpformed by anchoring a gold ball formed with the discharge onto thesecond bonding pad provided on the substrate. The stud bumper is tallerand softer than a plating bump and accordingly can deform plasticallyand easily advance and enter into the clearance between the bumpsprovided on the semiconductor chip.

[0015] Preferably, the semiconductor chip is faced down when it ismounted, and then heat and pressure are added to cause the bump formedon the substrate to plastically deform and then advance and enter intothe clearance between the bumps formed on the semiconductor chip.Applying heat and pressure enables the bump formed on the substrate tosurely cause plastic deformation and then advance and enter into theclearance between the bumps provided on the semiconductor chip.

[0016] Preferably, the semiconductor chip is faced down when it ismounted, and then heat, pressure, and ultrasonic vibration are added tocause the bump formed on the substrate to plastically deform and thenadvance and enter into the clearance between the bumps formed on thesemiconductor chip. This is effective in reducing the heatingtemperature level and forming a strong and stable metallic bondingbetween the bump and a bump surface within a short bonding time.

[0017] Preferably, a space intervening between the semiconductor chipand the substrate is filled with an underfill member. The underfillmember is, for example, an adhesive. The packaging according to thisinvention can leave a relatively large gap between the semiconductorchip and the substrate. Thus, it becomes possible to fill theintervening space with a sufficient amount of underfill member. Hence,it becomes possible to reduce a concentrated stress acting on a bumpbonding portion when a relative displacement between the semiconductorchip and the substrate is caused due to their thermal expansioncoefficient difference. In other words, the underfill member assures asufficient stress relaxing capability, and thus the bonding reliabilitycan be improved.

[0018] Preferably, the substrate is a circuit substrate. Alternatively,it is preferable that the substrate is an interposer substrate of asemiconductor package.

[0019] To accomplish the above-described and other related objects, thepresent invention provides a second flip chip packaging structureincluding a bump formed on a first bonding pad provided on a surface ofa semiconductor chip and a second bonding pad provided on a substrate,wherein the first and second bonding pads are mutually connected byelectrically and mechanically bonding the first and second bonding padsvia the bump under a condition that the bump formed on the semiconductorchip is adjusted in position relative to the second bonding pad providedon the substrate, wherein the second bonding pad provided on thesubstrate has a through hole or a recess, and the second bonding pad isbonded to the bump via an inner surface of the through hole or therecess.

[0020] According to this arrangement, the bonding pad provided on thesubstrate has an increased bonding area. Furthermore, at least part of aformed bonding surface is not parallel to a shearing direction of athermal stress to be produced due to thermal expansion coefficientdifference between the substrate and the semiconductor chip. Thus, itbecomes possible to improve the bonding reliability between thesemiconductor chip and the substrate.

[0021] According to this flip chip packaging structure, it is preferablethat the substrate is an interposer substrate of a semiconductorpackage. In this case, it is preferable that lands are disposed on onesurface of the interposer substrate and electro-conductive balls areformed on the lands to bond respective lands to corresponding lands ofan associated circuit substrate so as to constitute a ball grid array.Furthermore, it is preferable that the substrate is a circuit substrate.

[0022] Furthermore, it is preferable that the through hole or the recessis formed by etching. This is advantageous in accurately positioning andsimply forming the through hole or recess without substantially changingthe manufacturing processes of the substrate which are generally used.

[0023] Preferably, the bonding pad having the through hole or the recessis formed by plating. This is advantageous in that general manufacturingprocesses for forming a substrate can be used and it becomes possible toobtain a bonding pad whose upper surface is flat and stable in area.Obtaining a stable bonding area is feasible.

[0024] Preferably, the through hole or the recess is formed by a cuttingoperation using a drill or by a pressing operation using a die. This isadvantageous in accurately controlling the shape of the through hole orthe recess.

[0025] Preferably, the through hole or the recess is formed by atrimming operation using irradiation of a laser beam. This isadvantageous in accurately controlling the shape of the through hole orthe recess.

[0026] Preferably, the through hole or the recess has a notched shapeopened to an end surface of the bonding pad provided on the substrate.According to this arrangement, a vacant space in the through hole is nothermetically closed when such a space is left at the bottom of thethrough hole or the recess after accomplishing a bonding operation. Inother words, the bonding reliability is not lessened due to expansion orcontraction of a closed space occurring when the temperature changes.

[0027] Preferably, a plurality of through holes or recesses areprovided. This is advantageous in that the bonding area can be enlarged.

[0028] Furthermore, it is preferable that the bump is a stud bump formedby anchoring a gold ball formed with the discharge onto the firstbonding pad provided on the semiconductor chip. The stud bump is talland soft, and accordingly can deform largely. Hence, through the flipchip bonding operation, the bump surely causes plastic deformation andeasily bonds together with the through hole or recess of the bondingpad.

[0029] Preferably, the second bonding pad provided on the substrate andthe bump provided on the semiconductor chip are thermocompression bondedto each other under applied heat and pressure. Applying heat andpressure enables the bump to cause a plastic deformation so that thebump can extend in the through hole or recess so as to increase themetallic bonding surface.

[0030] Preferably, the bonding pad provided on the substrate and thebump provided on the semiconductor chip are bonded to each other underapplied heat, pressure, and ultrasonic vibration. Additionally using theultrasonic vibration is effective in reducing the time required for abonding operation. Furthermore, it becomes possible to realize alow-temperature bonding operation performed under relatively low heattemperatures.

[0031] Preferably, the bonding pad provided on the substrate and thebump provided on the semiconductor chip are bonded via an anisotropicconductive material. Electro-conductive particles contained in theanisotropic conductive material are easily trapped by the interfacebetween the bump and the through hole or recess. Thus, it becomespossible to obtain an adequate and stable bonding resistance.

[0032] Preferably, the bonding pad provided on the substrate and thebump provided on the semiconductor chip are bonded via anelectro-conductive material. The bonding area of the bonding padincreases when the conductive material advances and enters into thethrough hole or recess. The bonding reliability can be improved.

[0033] Furthermore, to accomplish the above and other related objects,the present invention provides a first method for forming a flip chippackaging structure comprising a step of providing at least twoapertures on a passivation film covering a first bonding pad provided ona semiconductor chip, a step of forming first bumps in respectiveapertures, a step of forming a second bump on a second bonding padprovided on a substrate, a step of adjusting the position of the firstbumps formed on the semiconductor chip relative to the second bumpprovided on the substrate, and a step of electrically and mechanicallybonding the first and second bonding pads via the first and second bumpsby causing the second bump provided on the second substrate toplastically deform and then enter into a clearance between the firstbumps provided on the semiconductor chip.

[0034] Preferably, the step of forming the first bumps on thesemiconductor chip is performed by plating.

[0035] Preferably, the second bump formed on the substrate is a studbump formed by anchoring a gold ball formed with the discharge onto thesecond bonding pad provided on the substrate.

[0036] Preferably, the first flip chip packaging method further includesa step of mounting the semiconductor chip facedown when it is packagedwith the substrate, and a step of applying heat and pressure (andultrasonic vibration) to cause the second bump formed on the substrateto plastically deform and then enter into the clearance between thefirst bumps formed on the semiconductor chip.

[0037] Preferably, the first flip chip packaging method further includesa step of filling a space intervening between the semiconductor chip andthe substrate with an underfill member.

[0038] Preferably, the substrate is a circuit substrate, or aninterposer substrate of a semiconductor package.

[0039] Furthermore, the present invention provides a second method forforming a flip chip packaging structure comprising a step of forming abump on a first bonding pad provided on a surface of a semiconductorchip, a step of forming a second bonding pad on a substrate, the secondbonding pad having a through hole or a recess, a step of adjusting theposition of the bump formed on the semiconductor chip relative to thesecond bonding pad provided on the substrate, and a step of electricallyand mechanically bonding the first and second bonding pads via the bumpby causing the bump to plastically deform and then enter into thethrough hole or the recess of the second bonding pad on a substrate.

[0040] Preferably, the substrate is an interposer substrate of asemiconductor package.

[0041] Preferably, lands are disposed on one surface of the interposersubstrate, and electro-conductive balls are formed on the lands to bondrespective lands to corresponding lands of an associated circuitsubstrate so as to constitute a ball grid array.

[0042] Preferably, the substrate is a circuit substrate.

[0043] Preferably, the step of forming the second bonding pad having thethrough hole or the recess is performed by etching or plating, or by acutting operation using a drill or by a pressing operation using a die,or by a trimming operation using irradiation of a laser beam.

[0044] Preferably, the through hole or the recess has a notched shapeopened to an end surface of the bonding pad provided on the substrate.

[0045] Preferably, a plurality of through holes or recesses areprovided.

[0046] Preferably, the bump is a stud bump formed by anchoring a goldball formed with the discharge onto the first bonding pad provided onthe semiconductor chip.

[0047] Preferably, the step of bonding the second bonding pad providedon the substrate and the bump provided on the semiconductor chip isperformed by thermocompression bonding under applied heat and pressure(and ultrasonic vibration).

[0048] Preferably, the step of bonding the bonding pad provided on thesubstrate and the bump provided on the semiconductor chip is performedby using an anisotropic conductive material or by using anelectro-conductive material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above and other objects, features and advantages of thepresent invention will become more apparent from the following detaileddescription which is to be read in conjunction with the accompanyingdrawings, in which:

[0050]FIG. 1 is a vertical cross-sectional view showing a semiconductordevice in accordance with a first embodiment of the present invention;

[0051]FIG. 2 is a vertical cross-sectional view showing a flip chippackaged portion in accordance with the first embodiment of the presentinvention;

[0052]FIG. 3 is a vertical cross-sectional view showing a pre-assembledcondition of components to be flip chip packaged in accordance with thefirst embodiment of the present invention;

[0053]FIG. 4A is a plan view showing a circuit substrate in accordancewith the first embodiment of the present invention;

[0054]FIG. 4B is a cross-sectional view showing the circuit substrate inaccordance with the first embodiment of the present invention, takenalong a line 4B-4B of FIG. 4A;

[0055]FIG. 5A is a plan view showing a semiconductor chip in accordancewith the first embodiment of the present invention;

[0056]FIG. 5B is a cross-sectional view showing the semiconductor chipin accordance with the first embodiment of the present invention, takenalong a line 5B-5B of FIG. 5A.

[0057]FIG. 6 is a vertical cross-sectional view showing the condition ofthe flip chip packaged portion immediately after the bonding operationis accomplished in accordance with the first embodiment of the presentinvention;

[0058]FIGS. 7A to 7D are plan views respectively showing a bumparrangement formed on the semiconductor chip in accordance with thefirst embodiment of the present invention;

[0059]FIG. 8 is a vertical cross-sectional view showing a modifiedsemiconductor device in accordance with the first embodiment of thepresent invention;

[0060]FIG. 9 is a vertical cross-sectional view showing a semiconductor30 device in accordance with a second embodiment of the presentinvention;

[0061]FIG. 10 is a vertical cross-sectional view showing a flip chippackaged portion in accordance with the second embodiment of the presentinvention;

[0062]FIG. 11A is a plan view showing a substrate in accordance with thesecond embodiment of the present invention;

[0063] FIG. FIG. 11B is a cross-sectional view showing the substrate inaccordance with the second embodiment of the present invention, takenalong a line 11B-11B of FIG. 11A;

[0064]FIGS. 12A to 12C are views explaining the processes for forming asubstrate bonding pad in accordance with the second embodiment of thepresent invention;

[0065]FIG. 13 is a vertical cross-sectional view showing a pre-assembledcondition of components to be flip chip packaged in accordance with thesecond embodiment of the present invention;

[0066]FIG. 14A is a plan view showing another substrate in accordancewith the second embodiment of the present invention;

[0067]FIG. 14B is a cross-sectional view showing the substrate inaccordance with the second embodiment of the present invention, takenalong a line 14B-14B of FIG. 14A;

[0068]FIG. 15A is a plan view showing another substrate in accordancewith the second embodiment of the present invention;

[0069]FIG. 15B is a cross-sectional view showing the substrate inaccordance with the second embodiment of the present invention, takenalong a line 15B-15B of FIG. 15A;

[0070]FIG. 16 is a vertical cross-sectional view showing a modified flipchip packaged portion in accordance with the second embodiment of thepresent invention;

[0071]FIG. 17 is a vertical cross-sectional view showing anothermodified flip chip packaged portion in accordance with the secondembodiment of the present invention;

[0072]FIG. 18 is a vertical cross-sectional view showing anothermodified flip chip packaged portion in accordance with the secondembodiment of the present invention;

[0073]FIG. 19 is a vertical cross-sectional view showing a conventionalflip chip packaged portion;

[0074]FIG. 20 is a vertical cross-sectional view showing anotherconventional flip chip packaged portion;

[0075]FIG. 21 is a vertical cross-sectional view showing anotherconventional flip chip packaged portion; and

[0076]FIGS. 22A to 22C are views explaining the processes for forming aconventional substrate bonding pad.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0077] Preferred embodiments of the present invention will be explainedhereinafter with reference to attached drawings.

First Embodiment

[0078] Hereinafter, a first embodiment of the present invention will beexplained with reference to attached drawings.

[0079]FIG. 1 is a vertical cross-sectional view showing a semiconductordevice in accordance with the first embodiment of the present invention.A semiconductor chip 10 is flip chip packaged on a circuit substrate 1.More specifically, under a condition that a bump 15 provided on thesemiconductor chip 10 is adjusted in position relative to a bonding pad2 provided on the circuit substrate 1, a bonding pad 12 provided on thesemiconductor chip and the bonding pad 2 provided on the substrate areelectrically and mechanically bonded to each other via the bump 15. FIG.2 is a vertical cross-sectional view showing a flip chip packagedportion. FIG. 3 shows a pre-assembled condition of the circuit substrate1 and the semiconductor chip 10. FIG. 4 shows the circuit substrate 1which is not packaged yet. Furthermore, FIG. 5 shows only thesemiconductor chip 10.

[0080] The semiconductor device of this embodiment is incorporated in anautomotive electronic control apparatus which is usually installed in anengine room, and is accordingly subjected to severe temperatureenvironment.

[0081] In FIG. 5, an insulation film 11 is formed in an upper surface ofthe semiconductor chip 10. A bonding pad 12 is formed on an insulationfilm 11. The bonding pad 12 has substantially a square shape. Apassivation film 13, formed on the insulation film 11, covers the pad12. More specifically, the passivation film 13 is formed as an outersurface of the semiconductor chip 10. The passivation film 13 coveringthe bonding pad 12 of the semiconductor chip 10 has two apertures 13 aand 13 b which are provided with barrier metals 14 a and 14 b. Two bumps15 a and 15 b are formed on the barrier metals 14 a and 14 b,respectively. Namely, the bumps 15 a and 15 b are formed via barriermetal 14 a and 14 b on the bonding pad 12 provided on the surface ofsemiconductor chip 10. Each of the apertures 13 a and 13 b isrectangular and extends in the same direction. In other words, theapertures 13 a and 13 b are parallel to each other. Accordingly, each ofthe bumps 15 a and 15 b is rectangular. These bumps 15 a and 15 b aredisposed in parallel to each other. A clearance S1 is provided betweenthe bumps 15 a and 15 b. The center of clearance S1 agrees with thecenter of the pad 12 provided on the semiconductor chip 10.

[0082] The passivation film 13 is a silicon dioxide film (i.e. SiO₂) ora silicon nitride film (i.e. SiN). The barrier metals 14 a and 14 b arenickel (i.e. Ni). The bumps 15 a and 15 b are gold (i.e. Au).

[0083] On the other hand, as shown in FIG. 4, the bonding pad 2 isformed on the circuit substrate 1. A bump 3 is formed on bonding pad 2provided on the substrate. The bump 3 is a stud bump which is formed bypress welding (anchoring) a gold ball formed with the discharge onto thebonding pad 2.

[0084] As shown in FIGS. 1 and 2, a space intervening between thesemiconductor chip 10 and the circuit substrate 1 is filled with anunderfill member (or an underfill adhesive) 20 which is for example madeof an epoxy or other thermosetting resin.

[0085] First of all, in a practical packaging operation, the bump 3provided on the substrate 1 is adjusted in position relative to thebumps 15 a and 15 b provided on the semiconductor chip as shown in FIG.3. From this condition, the bump 3 provided on the substrate plasticallydeforms under applied heat and pressure. The deformed bump 3 provided onthe substrate 1 thus advances and enters into the clearance S1 betweenthe bumps 15 a and 15 b provided on the semiconductor chip as shown inFIG. 6. More specifically, in bonding the bumps 15 a and 15 b providedon the semiconductor chip 10 with the bump 3 provided on the substrate1, the semiconductor chip 10 is first faced down against the substrate1. Then, the applied heat and pressure cause plastic deformation of thebump 3 provided on the substrate. And, the deformed bump 3 enters intothe clearance S1 between the bumps 15 a and 15 b provided on thesemiconductor chip 10, thereby accomplishing the bonding operationbetween the semiconductor chip and the circuit substrate. Applying heatand pressure is effective in surely or forcibly causing the bump 3 toplastically deform and enter into the clearance S1.

[0086] Thereafter, as shown in FIGS. 1 and 2, the space interveningbetween the semiconductor chip 10 and the circuit substrate 1 is filledwith the underfill member 20.

[0087] As shown in FIG. 2, the three-dimensional bonding surface beingthus obtained has an increased bonding area and includes a bondingsurface not parallel to a shearing direction X of the thermal stress tobe produced due to a thermal expansion coefficient difference betweenthe circuit substrate 1 and the semiconductor chip 10. Furthermore,compared with a case that no bump is provided on the substrate and thechip 10 has the bumps 15 a and 15 b, it is possible to enlarge the gap(distance) between the semiconductor chip 10 and the substrate 1 (referto FIG. 19). In other words, the stress relaxing capability of theunderfill member 20 can be enhanced. The bonding reliability can beimproved remarkably.

[0088] Namely, in the structure for flip chip bonding the faced-downsemiconductor chip 10 on the substrate 1, the bump 3 is formed on thepad 2 of the substrate 1 as a bonding member to be faced toward thesemiconductor chip 10. Furthermore, at least two bumps (15 a, 15 b) areformed on one pad 12 provided on the active face of the semiconductorchip 10 as bonding members to be faced toward the substrate 1. Accordingto this arrangement, a large gap G is provided between the semiconductorchip 10 and the substrate 1 after the bonding operation is accomplished.Furthermore, a large bonding area is provided. Furthermore, it ispossible to form a bonding surface which is not parallel to the shearingdirection X of the thermal stress to be produced due to a thermalexpansion coefficient difference between the substrate 1 and thesemiconductor chip 10. Thus, the bonding reliability can be remarkablyimproved.

[0089] In the arrangement shown in FIGS. 5A and 5B, the bumps 15 a and15 b provided on the semiconductor chip 10 can be formed by plating.This is advantageous in that the formed bumps are accurate in shape.Accordingly, the formed clearance S1 is accurate. The optimum size ofclearance S1 (i.e. gap L2 between two bumps) is in the range from 20% to40% of one side L1 of the square pad 12 provided on the semiconductorchip 10 or in the range from 15 μm to 30 μm. This optimized size isdetermined considering such conditions that the bonding area of theupper surface of respective bumps 15 a and 15 b can be enlarged and thebump 3 provided on the substrate can easily and surely enter into theclearance S1.

[0090] On the other hand, according to the arrangement shown in FIGS. 4Aand 4B, the bump 3 provided on the substrate 1 is a stud bump which isformed by press welding (anchoring) a gold ball formed with thedischarge onto the pad 2 provided on the substrate under given heat orultrasonic wave. The bump 3 can plastically deform and easily enter intothe clearance S1 between the bumps 15 a and 15 b provided on thesemiconductor chip 10, because the stud bump is tall and soft comparedwith a plating bump.

[0091] As described above, this embodiment forms the bump 3 on thebonding pad 2 provided on the substrate and opens at least two apertures13 a and 13 b on the passivation film 13 covering the bonding pad 12provided on the semiconductor chip 10, and further forms the bumps 15 aand 15 b in respective apertures 13 a and 13 b. Then, this embodimentcauses the bump 3 provided on the substrate 1 to advance and enter intothe clearance S1 between the bumps 15 a and 15 b provided on thesemiconductor chip.

[0092] In this manner, the bump 3 provided on the substrate enters intothe clearance S1 between the bumps 1 5 a and 1 5 b provided on thesemiconductor chip. This embodiment provides a three-dimensional bondingsurface having a large bonding area. Furthermore, the embodiment canform a bonding surface not parallel to the shearing direction X of thethermal stress to be produced due to a thermal expansion coefficientdifference between the substrate 1 and the semiconductor chip 10. Thebonding reliability between the semiconductor chip and the substrate canbe remarkably improved.

[0093] Furthermore, as shown in FIGS. 2 and 6, this embodiment canprovide a large gap G between the semiconductor chip 10 and thesubstrate 1 after the packaging operation is accomplished. Therefore,the space intervening between the circuit substrate 1 and thesemiconductor chip 10 is filled with a sufficient amount of underfillmember 20. Thus, this embodiment can reduce a concentrated stress actingon a bump bonding portion when a relative displacement between thesemiconductor chip 10 and the substrate 1 is caused due to their thermalexpansion coefficient difference. In other words, the underfill member20 is thick enough to assure a sufficient stress relaxing capability,and thus the bonding reliability can be improved.

[0094] According to the arrangement shown in FIG. 6, this embodimentapplies heat and pressure to facilitate the bonding between the bump 3provided on the substrate 1 and the bumps 15 a and 15 b provided on thesemiconductor chip 10. The bump 3 provided on the substrate 1 causesplastic deformation sufficiently and smoothly advance and enter into theclearance S1 between the bumps 15 a and 15 b provided on thesemiconductor chip 10. However, this embodiment can use an alternativemethod. For example, after the faced down semiconductor chip 10 ismounted on the substrate, it is possible to apply ultrasonic vibrationto the semiconductor chip 10 in addition to heat and pressure to causethe bump 3 provided on the substrate to deform plastically and thenadvance and enter into the clearance S1 between the bumps 15 a and 15 bprovided on the semiconductor chip. This is advantageous in lowering theheating temperature level. A strong and stable metallic bonding isformed along the surface between the bump 3 and respective bumps 15 aand 15 b within a relatively short bonding time.

[0095] A preferable temperature range for the thermocompression bondingis in the range from 200° C. to 300° C. A preferable temperature rangefor the ultrasonic bonding is in the range from 100° C. to 200° C. Ingeneral, the damage added to the semiconductor chip 10 decreases when alowering heating temperature is used during the bonding process. Forexample, it is now assumed that the pad 12 provided on the semiconductorchip 10 has the size of 100 μm in vertical and lateral directions (referto L1 shown in FIGS. 5A and 5B) and the bump (i.e. stud bump) 3 formedon the pad 2 provided on the substrate 1 has the diameter of 90 μm(refer to Φ1 shown in FIGS. 4A and 4B). In this case, the pressureapplied during the ultrasonic bonding is in the range from 40 gf to 80gf per bump provided on the substrate. The frequency of the ultrasonicwave is in the range from 40 kHz to 60 kHz. The amplitude of theultrasonic wave is in the range from 1 μm to 5 μm. The oscillation timeof the ultrasonic wave is in the range from 400 μms to 1000 ms.

[0096] According to the arrangement shown in FIGS. 5A and 5B, only tworectangular apertures 13 a and 13 b and corresponding two bumps 15 a and15 b are provided. However, it is possible to adopt other arrangementsshown in FIGS. 7A to 7D. The arrangement shown in FIG. 7A shows foursquare bumps 15 a to 15 d. The arrangement shown in FIG. 7B showssixteen square bumps 15 a to 15 q arranged in vertical and lateraldirections. The arrangement shown in FIG. 7C shows two bumps 15 a and 15b each having a half annular ring shape. The arrangement shown in FIG.7D shows four bump 15 a to 15 d each having a quarter annular ringshape.

[0097] According to the arrangement shown in FIG. 1, the semiconductorchip 10 is directly mounted on the circuit substrate 1 without beingpackaged beforehand. However, as an alternative arrangement, it ispreferable to use an interposer substrate 30 of a semiconductor packageas shown in FIG. 8. According to the arrangement shown in FIG. 8, theinterposer substrate 30 has one surface (i.e. upper surface) on whichthe semiconductor chip 10 is mounted and the opposite surface (i.e.lower surface) on which numerous lands 31 are formed as bonding membersto be faced toward a circuit substrate 40. Similarly, numerous lands 41are formed on the circuit substrate 40 as bonding members to be facedtoward the semiconductor package. The lands 31 of the interposersubstrate 30 and the lands 41 of the circuit substrate 40 aremechanically and electrically bonded by using a solder or any otherelectro-conductive paste 35. Alternatively, it is preferable that asolder ball is mounted beforehand on each land 31 on the interposersubstrate 30.

Second Embodiment

[0098] Next, a second embodiment of the present invention will beexplained.

[0099]FIG. 9 is a vertical cross-sectional view showing a semiconductordevice in accordance with the second embodiment of the presentinvention, according to which a semiconductor chip 60 is flip chippackaged on an interposer substrate 50. More specifically, under acondition that a bump 63 provided on the semiconductor chip 60 isadjusted in position relative to a bonding pad 51 provided on thesubstrate 50, a bonding pad 61 provided on the semiconductor chip 60 andthe bonding pad 51 provided on the substrate 50 are electrically andmechanically bonded to each other via the bump 63. FIG. 10 is a verticalcross-sectional view showing a flip chip packaged portion. FIGS. 11A and11B show only the semiconductor chip 50. The semiconductor device ofthis embodiment is incorporated in an automotive electronic controlapparatus which is usually installed in an engine room, and isaccordingly subjected to an environment with severe temperatures.

[0100] According to the arrangement shown in FIG. 9, the substrate 50 isan interposer substrate of a semiconductor package which has a lowersurface (i.e. the opposite surface) on which numerous lands 65 aredisposed so as to constitute a grid array as bonding members facingoutward. A solder or comparative electro-conductive ball 66 is disposedon each land 65 (i.e. land grid array) disposed on a circuit substratebonding surface of this interposer substrate 50. Theseelectro-conductive balls 66 constitute a ball grid array. Eachelectro-conductive ball 66 is a bonding member faced toward anassociated circuit substrate and to be bonded to a corresponding landformed on the associated circuit substrate. Furthermore, the uppersurface of the interposer substrate 50 is a semiconductor chip mountingsurface on which substrate bonding pads (i.e. electrodes provided on thesubstrate) 51 are formed. The semiconductor chip 60 is faced down whenit is mounted. On the other hand, chip bonding pads (i.e. electrodesprovided on the chip) 61 are formed on a surface (i.e. lower surface) ofsemiconductor chip 60 so as to agree in position with the correspondingpads 51 as shown in FIG. 10. A passivation film 62 is formed so as tocover respective pads 61. The passivation film 62 covering the pads 61has apertures where the bumps 63 are formed on the pad 61.

[0101] Furthermore, as shown in FIGS. 11A and 11B, the bonding pad 51provided on the substrate has a through hole 51 a. According to thearrangement shown in FIGS. 11BA and 11B, the through hole 51 a has anelongated shape. It is however preferable that the shape of the throughhole 51 a is circular or elliptic. The through hole 51 a is formed inthe following manner. First of all, as shown in FIG. 12A, a metal film52 is formed on the substrate 50. A resist (i.e. mask) 53, formed bypatterning, is disposed on the metal film 52. In this condition, theresist 53 has a through hole forming aperture 53 a. Then, as shown inFIG. 12B, the pad 51 (more specifically, the wiring pattern) is formedby etching the metal film 52 with the resist 53 disposed thereon. As aresult of this etching operation, the through hole 51 a is formed in thebonding pad 51 because of the presence of the through hole formingaperture 53 a extending vertically across the resist 53. The formedthrough hole 51 a has an inclined (tapered) sidewall. Finally, as shownin FIG. 12C, the resist (i.e. mask) 53 is removed. As a result, thethrough hole 51 a extending vertically in the bonding pad 51 is left onthe substrate.

[0102] Next, the packaging operation is performed in the followingmanner. As shown in FIG. 13, a first process is adjusting the mutualposition between the bonding pad 51 provided on the substrate and thebump 63 provided on the semiconductor chip. In this condition, as shownin FIG. 10, a process of deforming the bump 63 is performed to cause thebump 63 advance and enter into the through hole 51 a of the bonding pad51 provided on the substrate. As the flip chip bonding method, thisembodiment uses a method of thermocompression bonding the bonding pad 51and the bump 63 under applied heat and pressure.

[0103] According to the arrangement shown in FIG. 13, in the process offlip chip packaging the bonding pad 51 formed on interposer substrate 50with the semiconductor chip 60 mounting the bump 63 formed on its activeface, the center of the through hole 51 a formed in the bonding pad 51is located so as to agree with a bonding point (i.e. the center) of thebump 63. The diameter Φ11 of the through hole 51 a is smaller than themaximum diameter Φ10 of the bump 63. According to this arrangement, thebonding surface 30 between the bonding pad 51 and the bump 63 extendsalong an inclined surface of the side wall of the through hole 51 a. Thebonding area between the bonding pad 51 and the bump 63 is large.Furthermore, according to the arrangement shown in FIG. 10, it ispossible to form a bonding surface not parallel to the shearingdirection X of a thermal stress to be produced due to a thermalexpansion coefficient difference between the interposer substrate 5 andthe semiconductor chip 60. The bonding reliability can be remarkablyimproved.

[0104] The etching operation makes it possible to form the through hole51 a together with the wiring pattern as shown in FIGS. 12A to 12C. Itis not necessary to change or modify the manufacturing processes for ageneral interposer substrate. It is possible to accurately and simplyform the through hole 51 a. In this etching operation, as describedpreviously, positioning of the through hole 51 a is carried out so thatthe center of the through hole 51 a agrees with the bonding point of thebump 63. The through hole 51 a has the diameter Φ11 that is smaller thanthe maximum diameter Φ10 of the bump 63 as shown in FIG. 13. During theflip chip bonding operation, the bump 63 plastically deforms and theinside space of the through hole 51 a is filled with the deformed bump63.

[0105] Furthermore, the bonding pad 51 provided on the substrate and thebump 63 provided on the semiconductor chip are thermocompression bondedunder applied heat and pressure. Applying heat and pressure enables thebump 63 to quickly cause the plastic deformation and smoothly move intothe through hole 51 a, which surely increases the metallic bondingsurface.

[0106] Next, the second embodiment will be explained in comparison withthe prior art shown in FIGS. 19 to 22.

[0107] The flip chip bonding operation for a semiconductor chip can beexplained with reference to FIG. 19. First, the bump 112 is formed onthe active face of the semiconductor chip 110. Then, the bump 112 isconnected with the bonding pad 101 provided on the interposer substrate100 by thermocompression bonding or ultrasonic welding. Alternatively,as shown in FIG. 20, the bump 112 can be bonded with the bonding pad 101provided on the interposer substrate 100 by using electro-conductiveparticles 131 contained in an anisotropic conductive material 130.Furthermore, as shown in FIG. 21, the bump 112 can be bonded with thebonding pad 101 provided on the interposer substrate 100 by using anelectro-conductive material 140.

[0108] Furthermore, as a method of forming a wiring pattern (i.e.bonding pad) on the interposer substrate 100, it is possible to form afilm 150 serving as a wiring and form a mask 151 on this film 150 asshown in FIG. 22A. Subsequently, the film 150 serving as a wiring ispatterned with the mask 151 by etching so as to leave a pad 101 as shownin FIG. 22B. Finally, the mask 151 is removed as shown in FIG. 22C.

[0109] In the arrangement shown in FIG. 19, it is a recent trend thatthe semiconductor chip 110 is highly integrated and accordingly the size(i.e. electrode size) W1 of the pad 111 made of aluminum and a pitch(i.e. electrode size) P1 between two neighboring pads 111 are verysmall. When the semiconductor chip 110 is flip chip bonded to theinterposer substrate 100 via the bump 112, it is necessary to adjust thesize of the bonding pad 101 so as to correspond to the pitch (i.e.electrode size) P1 of the pad 111. The line width L of a wiring pattern(i.e. the width of the bonding pad 101 serving as part of the wiringpattern) formed on the interposer substrate 100 becomes small withdecreasing pitch between neighboring bonding pads 111 provided on thesemiconductor chip 110. The space S between neighboring lines becomessmall proportionally.

[0110] For example, it is now assumed that the semiconductor chip 110has the pad size (i.e. electrode size) W1 of 120 μm and the pitch P1 is200 μm. In this case, the bump has the size Φ20 of approximately 100 min diameter when the bump shape is circular (or in vertical/lateral sizewhen the bump shape is rectangular). The wiring pattern of theinterposer substrate 100 can be formed so as to satisfy the relationshipL/S=120 μm 80 μm. The width L of the bonding pad 101 is 120 μm. On theother hand, the method of using the etching for forming the wiringpattern as shown in FIGS. 22A to 22C is not expensive. According to thismethod, the wiring pattern has a trapezoidal shape in cross section. Thewidth of this wiring pattern at the bottom (i.e. lower surface) isdifferent from the width of the wiring pattern at the top (i.e. uppersurface). If the metal layer (150), such as Cu, forming the wiringpattern has the thickness of 15 μm, its width will be 100 μm at the topand 120 μm at the top. Accordingly, to obtain a satisfactory bondingarea, it is preferable that the bump 112 has the size of 100 μm so as toagree with the width (100 μm) of the upper surface of the bonding pad101.

[0111] On the other hand, it is now assumed that the pad 111 has thesize (i.e. electrode size) W1 of 90 μm and the pitch P1 of 110 μm. Inthis case, the bump size Φ20 is approximately 70 μm in diameter when thebump shape is circular (or in vertical/lateral size when the bump shapeis rectangular). If the wiring pattern of the interposer substrate 100is formed so as to satisfy the relationship L/S=60 μm/50 μm, the uppersurface of the bonding pad 101 will be 45 μm and accordingly it isdifficult to obtain a sufficient bonding area.

[0112] The method of using the plating for forming the wiring pattern isadvantageous in reducing the difference between the top width and thebottom width of the wiring pattern. However, the method of using theplating is expensive compared with the method of using the etching.Furthermore, even if the plating is used to form the wiring pattern, theupper surface of the bonding pad 101 will be 60μm to satisfy thepreviously described condition L/S=60/50. For example, when this deviceis installed in an automotive vehicle, it is impossible to obtain asufficient bonding area for satisfying the bonding reliability.

[0113] Furthermore, the bonding surface between the bonding pad 101 andthe bump 112 is parallel to the shearing direction X of a thermal stressto be produced due to a thermal expansion coefficient difference betweenthe interposer substrate 100 and the semiconductor chip 110. Therefore,the thermal stress possibly damages the bonding between them.

[0114] On the other hand, this embodiment forms the through hole 51 aextending vertically across the bonding pad 51 provided on the substrateas shown in FIGS. 14A and 14B. The inner surface of the through hole 51a can be used as a bonding portion to be bonded with the bump 63.

[0115] More specifically, as shown in FIG. 13, this embodiment forms thebonding pad 51 having the through hole 51 a on the interposer substrate50. The through hole 51 a of bonding pad 51 has the center agreeing withthe bonding point of the bump 63 and having the width Φ11 narrowercompared with the maximum diameter Φ of the bump 63. According to thearrangement of this embodiment, it is possible to increase the bondingarea between the bonding pad 51 and the bump 63 as shown in FIG. 10.Furthermore, according to the arrangement of this embodiment, it ispossible to form a bonding surface not parallel to the shearingdirection X of the thermal stress to be produced due to a thermalexpansion coefficient difference between the interposer substrate 50 andthe semiconductor chip 60. Thus, this embodiment can improve the bondingreliability between the semiconductor chip and the substrate.

[0116] Preferably, the bump 63 is a stud bump that is formed by placinga gold ball formed with the discharge onto the aluminum bonding pad (oran Au plating layer formed on an aluminum bonding pad) 61 formed on anactive face of the semiconductor chip 60 and anchoring this gold ballonto the bonding pad 61 under given heat or ultrasonic wave. The studbump is tall and soft compared with the plating bump and therefore candeform largely. Hence, through the flip chip bonding operation, the bump63 surely causes plastic deformation and easily bonds together with thethrough hole 51 a of the bonding pad 51.

[0117] Furthermore, instead of using the etching for forming the throughhole 51 a shown in FIG. 10, it is possible to use the pattern formationbased on the plating. Namely, the bonding pad 51 having the through hole51 a can be formed by plating. In this case, forming a hole in thebonding pad 51 so as to agree with the bonding center of the bump 63 canbe carried out during a manufacturing process of forming a generalinterposer substrate. In this case, a flat portion formed on the uppersurface of the bonding pad 51 is stable in its area, which stablyprovides the bonding area.

[0118] Furthermore, as another method of forming the through hole 51 a,a cutting operation using a drill or a press operation using a die canbe employed to mechanically form the through hole. Furthermore, thetrimming based on irradiation of a laser beam can be also used to formthe through hole. In any case, the through hole 51 a can be formedaccurately.

[0119] In this case, after forming the through hole 51 a by etching orpressing using a die, or trimming based on the laser irradiation, it ispreferable to form a nickel (Ni) plating base layer on the surface ofthe through hole 51 a and then form a gold (Au) plating layer or thelike on this base layer.

[0120] Furthermore, the through hole 51 a shown in FIGS. 11A and 11B canbe replaced with a recess. In this case, the insulation layer of theinterposer substrate 50 is not exposed in the bottom of the recess.Furthermore, the flat portion needs not be formed on the upper surfaceof the bonding pad 51.

[0121] The through hole 51 a shown in FIGS. 11A and 11B can be replacedwith a through hole 55 a shown in FIGS. 14A and 14B. According to thearrangement shown in FIGS. 11A and 11B, the outer circumferentialperiphery of the through hole 51 a is completely surrounded by a flattop surface of the pad 51. On the other hand, according to thearrangement shown in FIGS. 14A and 14B, the through hole 55 a (or arecess) has a notched shape opened to an end surface, i.e., inclinedouter side surface other than the flat top surface, of the bonding pad55 provided on the substrate. Using the notched through hole 55 a (or arecess) is advantageous in that a vacant space in the through hole 55 ais not hermetically closed when such a space is left at the bottom ofthe through hole 55 a (or recess) after a bonding operation isaccomplished. In other words, the bonding reliability is not lesseneddue to expansion or contraction of a closed space occurring when thetemperature changes. Furthermore, as shown in FIGS. 14A and 14B, in acase that the notched through hole 55 a (or recess) extends in the Ydirection, the bonding area can be stably obtained even when the bump 63dislocates in the Y direction relative to the through hole 55 a (orrecess) due to inaccuracy of the flip chip packaging operation.

[0122] Furthermore, the through hole 51 a shown in FIGS. 11A and 11B canbe replaced with through holes 56 a shown in FIGS. 15a and 15B.According to the arrangement shown in FIGS. 15a and 15B, plural throughhole 56 a (or recesses) are formed against a single pad 56. In thiscase, the bonding area can be further increased.

[0123] Furthermore, as shown in FIG. 16, this embodiment can be appliedto an arrangement including no interposer substrate for packaging thesemiconductor chip 60 with a circuit substrate 80. In other words, thesubstrate of this arrangement can be used as the circuit substrate 80.According to the arrangement shown in FIG. 16, the chip bonding pad(i.e. chip electrode) 61 provided on the semiconductor chip 60 iselectrically and mechanically bonded via the bump 63 with a bonding pad(substrate electrode) 81 provided on the circuit substrate 80. A throughhole 81 a (or recess) of the bonding pad 81 provided on the circuitsubstrate 80 brings the effect of increasing the bonding area.

[0124] According to the arrangement shown in FIG. 13, the bump 63provided on the semiconductor chip is thermocompression bonded with thebonding pad 51 provided on the substrate under applied heat andpressure. However, as another flip chip bonding method, it is preferableto use ultrasonic vibration in addition to heat and pressure. Themetallic bonding will be accomplished at lower temperatures within arelatively short time. Using the ultrasonic wave is advantageous in thatthe bonding time can be shortened. Furthermore, it becomes possible torealize a low-temperature bonding operation capable of suppressing theheating temperature.

[0125] Furthermore, as shown in FIG. 17, it is possible to use ananisotropic conductive material 71 as a bonding member. According tothis arrangement, a large interface is provided between the through hole81 a and the bump 63, which can easily trap electro-conductive particles72 contained in the anisotropic conductive material 71. Thus, anadequate and stable bonding resistance is obtained. Furthermore, asshown in FIG. 18, it is preferable to use an electro-conductive material90, such as a solder paste or a silver (Ag) paste. Even in this case,the bonding area of the bonding pad 81 is large because the conductivematerial 90 enters into the through hole 81 a. The bonding reliabilitycan be improved.

[0126] In any of the thermocompression bonding, the ultrasonic welding,and the bonding using the conductive material 90, it is desirable tofill the space interposing the semiconductor chip and the substrate withan underfill member or an adhesive (epoxy or comparable thermosettingresin) 70 to reinforce the bonding portion.

What is claimed is:
 1. A flip chip packaging structure comprising a bumpformed on a first bonding pad provided on a surface of a semiconductorchip and a second bonding pad provided on a substrate, wherein saidfirst and second bonding pads are mutually connected by electrically andmechanically bonding said first and second bonding pads via said bumpunder a condition that said bump formed on said semiconductor chip isadjusted in position relative to said second bonding pad provided onsaid substrate, wherein a bump is formed on said second bonding padprovided on said substrate, at least two apertures are opened on apassivation film covering said first bonding pad provided on saidsemiconductor chip, bumps are formed in respective apertures, and saidbump provided on said substrate advances and enters into a clearancebetween said bumps provided on said semiconductor chip.
 2. The flip chippackaging structure in accordance with claim 1, wherein said bump formedon said semiconductor chip is a bump formed by plating.
 3. The flip chippackaging structure in accordance with claim 1, wherein said bump formedon said substrate is a stud bump formed by anchoring a gold ball formedwith the discharge onto said second bonding pad provided on saidsubstrate.
 4. The flip chip packaging structure in accordance with claim1, wherein said semiconductor chip is faced down when it is mounted, andthen heat and pressure are added to cause said bump formed on saidsubstrate to plastically deform and then enter into said clearancebetween said bumps formed on said semiconductor chip.
 5. The flip chippackaging structure in accordance with claim 1, wherein saidsemiconductor chip is faced down when it is mounted, and then heat,pressure, and ultrasonic vibration are added to cause said bump formedon said substrate to plastically deform and then enter into saidclearance between said bumps formed on said semiconductor chip.
 6. Theflip chip packaging structure in accordance with claim 1, wherein aspace intervening between said semiconductor chip and said substrate isfilled with an underfill member.
 7. The flip chip packaging structure inaccordance with claim 1, wherein said substrate is a circuit substrate.8. The flip chip packaging structure in accordance with claim 1, whereinsaid substrate is an interposer substrate of a semiconductor package. 9.A flip chip packaging structure comprising a bump formed on a firstbonding pad provided on a surface of a semiconductor chip and a secondbonding pad provided on a substrate, wherein said first and secondbonding pads are mutually connected by electrically and mechanicallybonding said first and second bonding pads via said bump under acondition that said bump provided on said semiconductor chip is adjustedin position relative to said second bonding pad provided on saidsubstrate, wherein said second bonding pad provided on said substratehas a through hole or a recess, and said second bonding pad is bonded tosaid bump via an inner surface of said through hole or said recess. 10.The flip chip packaging structure in accordance with claim 9, whereinsaid substrate is an interposer substrate of a semiconductor package.11. The flip chip packaging structure in accordance with claim 10,wherein lands are disposed on one surface of said interposer substrate,and electro-conductive balls are formed on said lands to bond respectivelands to corresponding lands of an associated circuit substrate so as toconstitute a ball grid array.
 12. The flip chip packaging structure inaccordance with claim 9, wherein said substrate is a circuit substrate.13. The flip chip packaging structure in accordance with claim 9,wherein said through hole or said recess is formed by etching.
 14. Theflip chip packaging structure in accordance with claim 9, wherein saidsecond bonding pad having said through hole or said recess is formed byplating.
 15. The flip chip packaging structure in accordance with claim9, wherein said through hole or said recess is formed by a cuttingoperation using a drill or by a pressing operation using a die.
 16. Theflip chip packaging structure in accordance with claim 9, wherein saidthrough hole or said recess is formed by a trimming operation usingirradiation of a laser beam.
 17. The flip chip packaging structure inaccordance with claim 9, wherein said through hole or said recess has anotched shape opened to an end surface of said bonding pad provided onsaid substrate.
 18. The flip chip packaging structure in accordance withclaim 9, wherein a plurality of through holes or recesses are provided.19. The flip chip packaging structure in accordance with claim 9,wherein said bump is a stud bump formed by anchoring a gold ball formedwith the discharge onto said first bonding pad provided on saidsemiconductor chip.
 20. The flip chip packaging structure in accordancewith claim 9, wherein said second bonding pad provided on said substrateand said bump provided on said semiconductor chip are thermocompressionbonded to each other under applied heat and pressure.
 21. The flip chippackaging structure in accordance with claim 9, wherein said bonding padprovided on said substrate and said bump provided on said semiconductorchip are bonded to each other under applied heat, pressure, andultrasonic vibration.
 22. The flip chip packaging structure inaccordance with claim 9, wherein said bonding pad provided on saidsubstrate and said bump provided on said semiconductor chip are bondedvia an anisotropic conductive material.
 23. The flip chip packagingstructure in accordance with claim 9, wherein said bonding pad providedon said substrate and said bump provided on semiconductor chip arebonded via an electro-conductive material.
 24. A method for forming aflip chip packaging structure comprising the steps of: providing atleast two apertures on a passivation film covering a first bonding padprovided on a semiconductor chip; forming first bumps in respectiveapertures; forming a second bump on a second bonding pad provided on asubstrate; adjusting the position of said first bumps formed on saidsemiconductor chip relative to said second bump provided on saidsubstrate; and electrically and mechanically bonding said first andsecond bonding pads via said first and second bumps by causing saidsecond bump provided on said second substrate to plastically deform andthen enter into a clearance between said first bumps provided on saidsemiconductor chip.
 25. The flip chip packaging method in accordancewith claim 24, wherein the step of forming said first bumps on saidsemiconductor chip is performed by plating.
 26. The flip chip packagingmethod in accordance with claim 24, wherein said second bump formed onsaid substrate is a stud bump formed by anchoring a gold ball formedwith the discharge onto said second bonding pad provided on saidsubstrate.
 27. The flip chip packaging method in accordance with claim24, further comprising a step of mounting said semiconductor chipfacedown when it is packaged with said substrate, and a step of applyingheat and pressure to cause said second bump formed on said substrate toplastically deform and then enter into said clearance between said firstbumps formed on said semiconductor chip.
 28. The flip chip packagingmethod in accordance with claim 24, further comprising a step ofmounting said semiconductor chip facedown when it is packaged with saidsubstrate, and a step of applying heat, pressure, and ultrasonicvibration to cause said second bump formed on said substrate toplastically deform and then enter into said clearance between said firstbumps formed on said semiconductor chip.
 29. The flip chip packagingmethod in accordance with claim 24, further comprising a step of fillinga space intervening between said semiconductor chip and said substratewith an underfill member.
 30. The flip chip packaging method inaccordance with claim 24, wherein said substrate is a circuit substrate.31. The flip chip packaging method in accordance with claim 24, whereinsaid substrate is an interposer substrate of a semiconductor package.32. A method for forming a flip chip packaging structure comprising thesteps of: forming a bump on a first bonding pad provided on a surface ofa semiconductor chip; forming a second bonding pad on a substrate, saidsecond bonding pad having a through hole or a recess; adjusting theposition of said bump formed on said semiconductor chip relative to saidsecond bonding pad provided on said substrate; and electrically andmechanically bonding said first and second bonding pads via said bump bycausing said bump to plastically deform and then enter into said throughhole or said recess of said second bonding pad on a substrate.
 33. Theflip chip packaging method in accordance with claim 32, wherein saidsubstrate is an interposer substrate of a semiconductor package.
 34. Theflip chip packaging method in accordance with claim 33, wherein landsare disposed on one surface of said interposer substrate, andelectro-conductive balls are formed on said lands to bond respectivelands to corresponding lands of an associated circuit substrate so as toconstitute a ball grid array.
 35. The flip chip packaging method inaccordance with claim 32, wherein said substrate is a circuit substrate.36. The flip chip packaging method in accordance with claim 32, whereinthe step of forming said second bonding pad having said through hole orsaid recess is performed by etching.
 37. The flip chip packaging methodin accordance with claim 32, wherein the step of forming said secondbonding pad having said through hole or said recess is performed byplating.
 38. The flip chip packaging method in accordance with claim 32,wherein the step of forming said second bonding pad having said throughhole or said recess is performed by a cutting operation using a drill orby a pressing operation using a die.
 39. The flip chip packaging methodin accordance with claim 32, wherein the step of forming said secondbonding pad having said through hole or said recess is performed by atrimming operation using irradiation of a laser beam.
 40. The flip chippackaging method in accordance with claim 32, wherein said through holeor said recess has a notched shape opened to an end surface of saidbonding pad provided on said substrate.
 41. The flip chip packagingmethod in accordance with claim 32, wherein a plurality of through holesor recesses are provided.
 42. The flip chip packaging method inaccordance with claim 32, wherein said bump is a stud bump formed byanchoring a gold ball formed with the discharge onto said first bondingpad provided on said semiconductor chip.
 43. The flip chip packagingmethod in accordance with claim 32, wherein the step of bonding saidsecond bonding pad provided on said substrate and said bump provided onsaid semiconductor chip is performed by thermocompression bonding underapplied heat and pressure.
 44. The flip chip packaging method inaccordance with claim 32, wherein the step of bonding said bonding padprovided on said substrate and said bump provided on said semiconductorchip is performed by applying heat, pressure, and ultrasonic vibration.45. The flip chip packaging method in accordance with claim 32, whereinthe step of bonding said bonding pad provided on said substrate and saidbump provided on said semiconductor chip is performed by using ananisotropic conductive material.
 46. The flip chip packaging method inaccordance with claim 32, wherein the step of bonding said bonding padprovided on said substrate and said bump provided on semiconductor chipis performed by using an electro-conductive material.